1. Field of the Invention
The present invention relates to a memory circuit, and in particular to the improvement of a word driver circuit in the memory circuit.
2. Related Arts
The development of a DRAM, etc., of which memory having a large capacity is fabricated on semiconductor substrate has been aggressively pursued. The memory having increased capacity have thus been employed so that, information processors, such as personal computers, with higher performance and higher processing speeds are being produced.
FIG. 6 is a circuit diagram illustrating a conventional word decoder and word driver for a DRAM. Generally, a plurality of sections called memory banks are provided on a semiconductor chip, with a plurality of memory cell blocks and sense amplifiers being provided in each of the memory bank areas. In FIG. 6 are shown a memory cell block 3 and an adjacent sense amplifier SA. A plurality of cell matrixes 4 are provided in the memory cell block 3. A plurality of word lines WL and a plurality of intersecting bit lines thereto (not shown) lie in the cell matrix 4. A memory cells (not shown) are located at each point of the intersection of the word lines and the bit lines.
Since a load of the word line have increased in accordance with the increased capacity of the recent memory, it is difficult for the word lines in the memory cell block 3 to be collectively driven by a single word driver, as in a conventional manner. To resolve this problem, the word lines are divided into a plurality of sub-word lines, with each sub-word line being driven by a sub-word driver SWD, which is provided adjacent to the cell matrix 4. In the example in FIG. 6, 256 word lines are provided in the memory cell block 3, a main word decoder 5 selects groups of four word lines among 256 word lines. And a sub-word decoder 6 selects one of the selected four word lines.
As is shown in FIG. 6, inverted and non-inverted main word selection signals MWX 0 and MWX 1, and MWZ 0 and MWZ 1, are output by the main word decoder 5. Sub-word selection signals SWD 0 through SWD 3 are output by the sub-word decoder 6. Address signals 7 and 8 are supplied by a predecoder to the decoders 5 and 6. The sub-word driver SWD receives the main word selection signals and the sub-word selection signals, and drives the sub-word lines in the selected row.
Thus, as is shown in FIG. 6, the areas for the sub-word drivers are provided between the cell matrixes 4 and adjacent to the cell matrixes 4 in the column direction. As memory capacity grows larger, the number of the sub-word lines is increased and the areas for the sub-word drivers driving them are also increased, giving rise to one of the problems accompanying the increase in memory capacity.
FIG. 7 is a detailed diagram illustrating the conventional sub-word driver shown in FIG. 6. FIG. 8 is a table for explaining the operation of the conventional sub-word driver. The sub-word driver in FIG. 7 is a CMOS circuit comprised by a P-channel transistor Q1 and N-channel transistors Q2 and Q3. The sub-word driver is connected to the sub-word line WL. BL represents a bit line and MC represents an example memory cell having a single transistor. The main word selection signal MWX is transmitted to the gate electrodes of the transistors Q1 and Q2, and the main word selection signal MWZ, which is an inverted signal thereto, is transmitted to the gate electrode of the transistor Q3. Further, sub-word selection signal SWP0 is supplied to the P channel transistor Q1 and the N channel transistor Q3.
The operation will be briefly described. First, when both the main word selection signal MWX, MWZ and the sub-word selection signal SWD0 are in a selected state, as is shown in FIG. 8, the selection signals MWX, MWZ and SWD0 are at level V.sub.ss (ground level), level V.sub.cc (power supply voltage level), and level SV.sub.c (higher level than power supply voltage level). As a result, the transistors Q1 and Q3 are rendered on, the transistor Q2 is rendered off, and the word line WL is driven to the high level SV.sub.c of the sub-word selection signal SWD0. When the main word selection signals MWX, MWZ are in selected state and the sub-word selection signal is in a non-selected state, the potentials of the signals are MWX=L, MWZ=H, SWO=l as shown in FIG. 8. As a result, since the sub-word selection signal SWD0 is reduced to level V.sub.ss (ground level), even though the P-channel transistor Q1 is in the ON state, the word line WL is at level L. However the potential of the word line WL can not be reduced to the point equal to or lower than the gate potential V.sub.ss of the transistor Q1 plus the threshold voltage Vth through the P-channel transistor Q1 only, and is in the floating state. Therefore, the N-channel transistor Q3 is additionally provided. The transistor Q3 is rendered on to ensure the clamping of the word line W to the level V.sub.ss of the sub-word selection signal SWD0.
When the main word selection signal is in the non-selected state, the main word selection signal MWX goes to level H and N-channel transistor Q2 is rendered on. The word line WL is therefore set to level V.sub.ss, regardless of the state of the sub-word selection signal SWD0.
As is described above, three transistors and the supply of three selection signals are required for the sub-word driver in FIG. 7.
In FIG. 9 is shown another example CMOS circuit for a conventional sub-word driver circuit. The table in FIG. 10 shows the levels of selection signals for explaining the operation of the sub-word driver. When a main word selection signal MNX is in the selected state, and a sub-word selection signals SWDZ, SWDX are in the selected state, the main word selection signal MWX is at level V.sub.ss (ground level), and a P-channel transistor Q4 is rendered on. A word line is driven at level SV.sub.c, higher than the power supply voltage V.sub.cc which is supplied to the sub-word selection signal SWDZ, and goes to level SV.sub.c. When the main word selection signal MWX is in the selected state, and the sub-word selection signals SWDZ, SWDX are the non-selected state, the sub-word selection signal SWDZ goes to level V.sub.ss and the word line WL is set to level L through the transistor Q4. As well as in FIG. 6, however, in accordance with the property of the P-channel transistor Q4, the potential of the word line WL is floating at a level obtained by adding the threshold voltage value to the potential level V.sub.ss of the gate electrode of the transistor Q4. Therefore, an N-channel transistor Q6 is provided as a clamping transistor to forcibly set the word line WL at level V.sub.ss.
Therefore, the work driver in FIG. 9 also requires three transistors and three control signals.
As previously described, when the word line is divided into sub-word lines each of which is driven by a sub-word driver, three transistors are required for the conventional sub-word driver and three selection signals must be supplied thereto.
As is shown in the area of the memory cell block 3 in FIG. 6, a plurality of sub-word drivers are positioned in the column direction, and three selection signals are supplied to each of the drivers. The dimensions of the area occupied by the circuits and their selection signal lines prevents the provision of a microstructure in according to the increased memory capacity.